中英
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locking circuit中文是什么意思
- 中文翻譯
- 造句
- 保持電路強制同步電路
- 閉合電路
- 鎖閉電路
- 鎖定電路
- 吸持電路
- 自保線路
- lock lock2 n. 1.一綹卷發(fā)。 〔pl.〕 ...
- circuit n. 1.(某一范圍的)周邊一圈；巡回，周游；巡回路線[ ...
- approach locking track circuit 接近鎖閉軌道電路
- automatic locking circuit 自動鎖定電路
- locking track circuit 鎖閉軌道電路
- phase locking circuit 相位同步電路
- route locking circuit 進路鎖閉電路
- sectional route locking circuit 進路分段鎖閉電路
- self-locking circuit 自鎖電路
- locking 打開或關閉文件共享鎖; 放映機卡住; 封鎖; 加鎖; 進閘; 洛金; 鎖閉; 鎖定同步堵塞; 鎖合; 鎖舞; 同步
- active locking 受迫模同步; 主動閉鎖
- advance locking 預先鎖閉
- air locking 密封材料; 氣密材料
- anal locking 鎖肛的
- approach locking 接近鎖閉; 接近鎖定裝置; 接近鎖緊
- automatic locking 自動鎖閉; 自動鎖定
- back locking 回閉鎖
- bar locking 鎖尺鎖閉
- beam locking 射束鎖定
- bridge locking 活動橋鎖閉
- castor locking 轉(zhuǎn)向輪的鎖定
- central locking 中控門鎖
- check locking 照查鎖閉
- clutch locking 離合器接合
- conditional locking 條件鎖閉
- Locking circuit board support cs - type at richeng
Pc板隔離柱cs - Rccn locking circuit board support cs - type material : ul approved nylon 66 , 94v - 2 by hand to support p . c . b
使用時先將基板鉆孔4 . 8mm后將隔離柱固定，再將p . c .板套入即可。 - Dds is used to achieve fine resolution , while injection phase lock circuit is used to realize low phase noise high performance input reference frequency
Dds用于實現(xiàn)小步進,而注入鎖相電路則用來產(chǎn)生低相噪的高性能參考源。 - Lut was replaced by the method taking triangle wave and differential in the line phase locked circuit , so it saves the hardware area and cost
在行鎖相中,用取三角波然后差分的方法替換了查找表,減小了芯片面積,降低了成本。 - Arranged signal activating lock circuit and time - base control circuit in the sound wave receiving circuit to take the initial signal of back wave as the valid one in the cycle , thus to improve the ratio of signal vs . noise and detective precision
在超聲波接收電路中設有信號觸發(fā)鎖定電路和時基控制電路。實現(xiàn)以各探頭中最早收到的回波信號為本檢測單元的有效信號，有效提高信噪比和檢測精度； 4 - Then according to the emphasis of the design , went deeply into the theory of pll frequency synthesizers widely used , described pll ’ s working principle , structure and several types in detail , and made research and analysis of pll frequency synthesizers ’ phase noise , including the effect of the active loop filter on the phase noise , and give some methods to make improvement as well , such as changing loop filter form , reducing divide number , and increase phase detector frequency , etc . then paper introduced the principle character and phase noise analysis of direct digital frequency synthesizer ( dds ) and injection phase lock circuit , which are also important circuits in the design
論文首先對幾十年頻率合成器的發(fā)展進行概述,而后針對本次設計的重點,對應用較為廣泛的鎖相頻率合成理論進行了深入的探討,詳細介紹了鎖相環(huán)的工作原理、組成結構和鎖相類型,并對鎖相頻率合成器的相噪特性進行了研究分析,包括有源環(huán)路濾波器對于相噪的影響,提出了改善相位噪聲的幾點措施:改善環(huán)路形式、降低分頻數(shù)、增大鑒相頻率等。接著介紹了直接數(shù)字頻率合成器( dds )和注入鎖相電路的原理特點以及相噪分析,它們也是本次設計的重要電路。 - The clock recovery block of usb2 . 0 transceiver macrocell consists of phase locked circuit , such as pll and dll ( delay locked loop ) . this block use external crystal 12mhz sin signal to produce 60mhz , 120mhz , 480mhz clock signal , and can recover colock signal form date wave . it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2 . 0 specification .
目的是用鎖相環(huán)電路? pll和dll (延遲鎖相環(huán))實現(xiàn)usb2 . 0收發(fā)器宏單元utm的時鐘恢復模塊。其中pll環(huán)路構成的時鐘發(fā)生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環(huán)路依據(jù)本地時鐘信號對外部數(shù)據(jù)信號進行時鐘恢復。
- locking circuitとは意味：保持回路｛ほじ かいろ｝
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